Clussys is a high-tech enterprise dedicated to building high-speed interconnect infrastructure for chips. We provide data centers, cloud providers, server OEMs, and telecom operators with advanced high-speed interconnect algorithms, chips, and customized hardware system solutions.
Clussys is committed to becoming a global leader in server architecture, focused on high-performance chip interconnect infrastructure for AI computing. Through continuous technological innovation and outstanding product development, we deliver faster and more reliable interconnect solutions for customers, driving intelligent upgrades across the industry.
Leveraging a standardized PCIe interface, CXL technology enables efficient interconnection between CPUs and between CPUs and accelerators. Clussys has introduced an 8-way CPU interconnect verification solution based on CXL, significantly reducing the cost and complexity of developing multi-processor servers. Additionally, the company has released a PCIe/Ethernet converged distributed storage solution that breaks through the limitations of traditional storage in terms of density and power consumption, offering scalable, cost-effective, and energy-efficient storage expansion for large-scale data centers.
The rapid development of large AI models has led to a surge in computing power demand, which can no longer be met by a single chip. This necessitates clustering multiple GPU or AI chips. As advanced process nodes face limitations and Moore’s Law gradually loses effectiveness, multi-GPU interconnect becomes critical. UALink protocol has attracted widespread attention for its minimalist design and open ecosystem, aiming to tackle technical challenges such as ultra-high speed and ultra-large bandwidth in GPU interconnect.
Built on CXL technology and the self-developed SVBM inference optimization engine to run large-parameter models locally at lower hardware cost; ships with a multi-agent orchestration engine and mainstream model serving, supports RAG knowledge augmentation, keeps data on-premises, ready out of the box.
Pools memory across nodes over the CXL protocol and allocates it on demand, with tiered KV Cache storage and cross-instance sharing to break the "memory wall".
Attaches external GPU compute to existing devices through high-speed interfaces for local LLM inference, image generation and vector retrieval, keeping data local and scaling on demand without replacing the machine.
Together the three form a complete product matrix of host, memory expansion and compute expansion.
Specializing in high-speed interconnect chips and system solution design.
CXL: Revolutionizing Multi-CPU and Memory Architectures
UALink: Breaking Through Multi-GPU Cluster Interconnect Bottlenecks
